Embodiments of the present invention relate to a high voltage input stage for a complementary metal oxide semiconductor (CMOS) differential amplifier.
High voltage differential amplifiers using relatively low voltage transistors require protection for differential input terminals to avoid gate oxide stress. Circuits of the prior art have typically used diode clamps to limit peak-to-peak voltage across differential input terminals. These diode clamps, however, conduct high currents under forward bias. Moreover, they increase input capacitance, may slow operation due to forward bias recovery time, and increase noise.
Referring to FIG. 1, there is a high voltage differential amplifier circuit of the prior art. Here, and in the following discussion the differential amplifier may be an operational amplifier or other balanced amplifier for amplifying difference signals. The circuit includes back-to-back diodes 102 and 104 connected between differential input terminals Vin+ and Vin−. The input terminals are connected directly to the gate terminals of low voltage p-channel input transistors 106 and 108. A common source terminal of p-channel transistors 106 and 108 is connected to current source 100. The drain terminals of p-channel transistors 106 and 108 are connected to negative and positive input terminals of differential amplifier 110, respectively. In operation, peak-to-peak voltage between input terminals Vin+ and Vin− is limited to a diode drop of approximately 0.7 V plus a voltage developed across the parasitic resistance of the forward biased diode. The circuit of FIG. 1, therefore, protects low voltage p-channel transistors 106 and 108 at the expense of high forward bias diode current, high capacitance, and additional noise.
Referring next to FIG. 2, there is another high voltage differential amplifier circuit of the prior art. This circuit includes p-channel switch transistors 202 and 204 and p-channel input transistors 206 and 208, having control gates coupled to respective input terminals Vin+ and Vin−. Current sources 200 are coupled to the respective common source terminals of the p-channel transistors. Drain terminals of p-channel transistors 206 and 208 are coupled to negative and positive input terminals of differential amplifier 210, respectively. In operation, when input terminal Vin− is held to 0 V, for example, p-channel transistors and 204 and 208 remain on. A high positive voltage applied to input terminal
Vin+ turns off p-channel transistors 202 and 206. In this condition, the common source and bulk terminals of p-channel transistors 202 and 206 are driven high by current source 200. P-channel transistor 204 remains on and drives the common drain terminal of p-channel transistors 202 and 204 high. The drain terminal of p-channel transistor 206 is essentially floating. Thus, there is insufficient voltage across the gate oxide of p-channel transistors 202 and 206 to damage gate oxide. However, there are several disadvantages to this circuit. First, transconductance of the input terminals is reduced by resistance of p-channel switch transistors 202 and 204. This increases noise and offset voltage and decreases bandwidth of the differential amplifier.
While the preceding approaches protect low voltage input transistors, the present inventors recognize that still further improvements are possible. Accordingly, the preferred embodiments described below are directed toward improving upon the prior art.